The present invention relates to a semiconductor device. In particular, the present invention relates to a technique effective when used for a semiconductor device having a face up structure.
Semiconductor devices which are integrated in small-sized electronic equipment such as mobile phone, portable information processing terminal equipment or portable personal computer are requested to be thinner and smaller and have more pins. As semiconductor devices satisfying such requirements, CSP (Chip Size Package or Chip Scale Package) type ones have been developed for example. CSP type semiconductor devices having various structures have been proposed and already industrialized, but among them, those having a face up structure which can be produced at a low cost using an existing plant are most popular.
The CSP type semiconductors having a face up structure each principally comprises a substrate (interconnection (wiring)substrate) having an interconnection(wiring) formed on a chip mounting surface which is the first surface (one main surface) of first and second surfaces (one main surface and the other main surface which are opposite to each other), a semiconductor chip being mounted on the chip mounting surface of the substrate and having an electrode (bonding pad) formed on a circuit forming surface which is the first surface (one main surface) of first and second surfaces (one main surface and the other main surface which are opposite to each other), a conductive wire (bonding wire) for electrically connecting the electrode of the semiconductor chip and the interconnection of the substrate, a resin sealing body (resin body) for sealing therewith the semiconductor chip, wire and the like, and a bump electrode (external terminal) disposed on the second surface of the substrate as an externally connecting terminal. The interconnection has a wire connecting pad (wire connection portion) disposed at the periphery of the substrate and a bump connecting land (bump connecting portion) disposed on the more internal side on the substrate than the wire connecting pad. The wire is connected, at one end thereof, with the electrode of the semiconductor chip and, at the other end thereof, with the wire connecting pad of the interconnection. The bump electrode is connected with a bump connecting land of the interconnection through a connecting hole (through hole) from the second surface (the other main surface) side of the substrate.
The CSP-type semiconductor device having a face up structure is described in, for example, xe2x80x9cElectronic Parts and Materials, September issue, pp. 22-52 (1998)xe2x80x9d published by Kogyo Chosakai.
The present inventors have investigated the above-described CSP type semiconductor device having a face up structure and found the below-described problems.
In the face up structure, a wire connecting pad is indispensable for interconnection, because an electrode formed on a circuit forming surface of a semiconductor chip and an interconnection formed on the chip mounting surface of a substrate are electrically connected via a conductive wire. Only one wire connecting pad is formed per interconnection, which does not cause a problem when an ordinarily-employed semiconductor chip of a predetermined external size is mounted. When a semiconductor chip has an external size smaller than that of an ordinary semiconductor chip, on the other hand, the length of the wire for connecting the electrode of the semiconductor chip with the wire connection pad of the interconnection increases with a decrease in the external size of the semiconductor chip, which worsens the sagging of the wire (sagging of the wire loop after bonding), leading to a tendency to cause inconveniences such as short-circuit between the wire and the interconnection in a wire bonding step for connecting the electrode of the semiconductor chip with the wire connecting pad of the interconnection via the wire. This tendency due to the worsening of the wire sagging is eminent particularly in the CSP type semiconductor, because the loop height (the height from the circuit forming surface of the semiconductor chip to the top portion perpendicular thereto) of the wire is lowered for making the semiconductor device thinner.
In a step for sealing the semiconductor chip, wire and the like with a resin sealing body by the transfer molding method, the wire flow tends to be caused by the insulating resin injected under pressure, leading to inconveniences such as short-circuit between two adjacent wires.
Inconveniences as described above markedly lower a production yield of the semiconductor device having, integrated therein, a semiconductor chip having a smaller external size than an ordinary semiconductor chip having a predetermined external size.
In addition, with an increase in the length of the wire, an inductance increases, which deteriorates electrical properties of the semiconductor device having, integrated therein, a semiconductor chip having an external size smaller than an ordinary semiconductor chip.
Such problems also tend to occur in the chip shrink for reducing the whole size of the semiconductor chip.
An object of the present invention is to provide a technique permitting the production of a semiconductor device having, integrated therein, a semiconductor chip of a smaller external size than an ordinary semiconductor chip without lowering a production yield.
Another object of the present invention is to provide a technique permitting the production of a semiconductor device having, integrated therein, a semiconductor chip of a smaller external size than an ordinary semiconductor chip without deteriorating electrical properties.
The above-described and the other objects and novel features of the present invention will be apparent by the description herein and accompanying drawings.
Among the inventions disclosed by the present application, summaries of the representative ones will next be described briefly.
(1) A semiconductor device which is formed to have a square plane and has a substrate having an interconnection formed on the first surface (chip mounting surface) of first and second opposite surfaces, a semiconductor chip which is mounted on the first surface of the substrate and has an electrode formed on the first surface (circuit forming surface) of first and second opposite surfaces and a conductive wire for electrically connecting the electrode of the semiconductor chip and the interconnection of the substrate,
wherein the interconnection has a plurality of wire connecting pads which are arranged from the peripheral side toward the inner side of the substrate.
(2) A semiconductor device which is formed to have a square plane and has a substrate having an interconnection formed on the first surface (chip mounting surface) of first and second opposite surfaces, a semiconductor chip which is mounted on the first surface side of the substrate and has an electrode formed on the first surface (circuit forming surface) of first and second opposite surfaces and a conductive wire for electrically connecting the electrode of the semiconductor chip and the interconnection of the substrate,
wherein the interconnection has a bump connecting land for connecting a bump electrode from the second surface side of the substrate and a plurality of wire connecting pads which are arranged from the peripheral side toward the inner side of the substrate.
(3) A semiconductor device which is formed to have a square plane and has a substrate having an interconnection formed on the first surface (chip mounting surface) of first and second opposite surfaces, a semiconductor chip which is mounted on the first surface side of the substrate and has an electrode formed on the first surface (circuit forming surface) of first and second opposite surfaces, a conductive wire for electrically connecting the electrode of the semiconductor chip and the interconnection of the substrate and a resin sealing body for sealing the semiconductor chip and the wire,
wherein the interconnection has a plurality of wire connecting pads which are arranged from the peripheral side toward the inner side of the substrate.
(4) A semiconductor device which is formed to have a square plane and has a substrate having an interconnection formed on the first surface (chip mounting surface) of first and second opposite surfaces, a semiconductor chip which is mounted on the first surface of the substrate and has an electrode formed on the first surface of first and second opposite surfaces, a conductive wire for electrically connecting the electrode of the semiconductor chip and the interconnection of the substrate and a resin sealing body for sealing therewith the semiconductor chip and the wire,
wherein the interconnection has a bump connecting land for connecting a bump electrode from the second surface side of the substrate and a plurality of wire connecting pads which are arranged from the peripheral side toward the inner side of the substrate.
According to the above-described means (1) or (2), when a semiconductor chip having an external size smaller than an ordinary semiconductor chip of a predetermined external size is integrated in a semiconductor, it is possible to select a proper wire connecting pad from those arranged from the peripheral side toward the inner side of the substrate so as to shorten the wire length according to the external size of the semiconductor chip, which makes it possible to suppress the wire length which otherwise increases with a decrease in the external size of the semiconductor chip, leading to suppression of an increase in the wire sagging. As a result, in the wire bonding step for connecting the electrode of the semiconductor chip with the wire connecting pad of the interconnection via a wire, short-circuit between the wire and the interconnection can be suppressed, which makes it possible to produce a semiconductor device without lowering the yield even when the semiconductor chip smaller in external size than the ordinary semiconductor chip is integrated.
According to the above-described means (3) or (4), when a semiconductor chip having an external size smaller than an ordinary semiconductor chip of a predetermined external size is integrated in a semiconductor, it is possible to select a proper wire connecting pad from those arranged from the peripheral side toward the inner side of the substrate so as to shorten the wire length according to the external size of the semiconductor chip, which makes it possible to suppress the wire length which otherwise increases with a decrease in the external size of the semiconductor chip, leading to suppression of an increase in the wire sagging. As a result, in the step for sealing the semiconductor chip and the wire with a resin sealing body, the flow of the wire caused by the insulating resin injected upon pressure can be suppressed and therefore, the occurrence of a short-circuit between two adjacent wires can be suppressed, which makes it possible to produce a semiconductor device without lowering the production yield even in the case where a semiconductor chip smaller in external size than an ordinary semiconductor chip is integrated.
According to any one of the above-described means (1) to (4), when a semiconductor chip having an external size smaller than an ordinary semiconductor chip of a predetermined external size is integrated in a semiconductor, it is possible to select a proper wire connecting pad from those arranged from the peripheral side toward the inner side of the substrate so as to shorten the wire length according to the external size of the semiconductor chip, which makes it possible to suppress the wire length which otherwise increases with a decrease in the external size of the semiconductor chip. As a result, an increase in the inductance can be suppressed, which makes it possible to produce a semiconductor device without deteriorating its electrical properties even in the case where a semiconductor chip smaller in external size than an ordinary semiconductor chip is integrated in it.